This invention relates to buffer circuits for converting from voltages appropriate for Complimentary Metal Oxide Silicon (CMOS) circuitry to voltages compatible with Emitter Coupled Logic (ECL) circuitry.
In many systems, especially those requiring high speed data links, a need exists to provide effective interconnection between integrated circuit chips employing CMOS technology and chips employing ECL circuitry. The problem arises because CMOS circuits generally operate with logic swings between 0.fwdarw.5 volts, while ECL chips operate with logic swings between -0.95.fwdarw.-1.7 volts.
A traditional method of achieving the appropriate voltage swing is to provide a bipolar buffer circuit in a chip which is external to the CMOS chip (see, e.g., Fairchild F100K ECL Data Book, pp. 3-38 to 3-40 (1986)). It would be more desirable based on performance and cost factors to provide a CMOS output buffer incorporated into the CMOS chip itself for interconnection chip.
Some suggestions have been made recently to provide a CMOS output buffer circuit. For example, in Meier, "A 2 .mu.m CMOS Digital Adaptive Equalizer Chip . . . ," IEEE International Solid State Circuits Conference Digest of Technical Papers, pp. 64-65 and 302-303 (1988), the lower level voltage is established by an external power supply. The upper voltage level is set by an MOS transistor acting as a current source which mirrors the current through a series of transistors in another branch. Thus, only the upper voltage level is controlled by the circuit.
It has also been proposed to provide the upper and lower voltages by coupling high and low reference voltages to the gates of separate transistors in separate branches of the buffer circuit. A third transistor controls whether one or both branches will be coupled to the buffer output thereby determining if the lower voltage level or upper voltage level is set. (See U.S. patent application Ser. No. 310,407 of P. C. Metz and R. L. Pritchett, Ser. No. 310,407, filed Feb. 13, 1989, which is incorporated by reference herein.)
It is an object of the invention to provide an alternative output buffer circuit as part of a CMOS integrated circuit chip for setting voltage levels for connection to ECL logic chips.